Parameterized Cache Designs (In-Progress)
Parameterized Direct Mapped, Fully Associative, and N-Way Associative Caches in SystemVerilog
SystemVerilogVivadoComputer Architecture
Projects
A collection of projects I've worked on, showcasing my skills and experience.
Floating-Point ALU for IEEE-754 Single-Precision Numbers
SystemVerilog-based design and FPGA implementation of a full-featured pipelined floating-point ALU
SystemVerilogRTL DesignIEEE-754Constrained-Random VerificationStatis Timing Analysis
6 Stage Pipeline RISC-V Cpu
SystemVerilog-based implementation of a RISC-V CPU core with a 6 stage pipeline and various pipeline optimizations
SystemVerilogRTL DesignComputer ArchitectureStatic Timing Analysis