Systolic Array-based Matrix Multiplier for Neural Networks
Systolic Array-based Matrix Multiplier for Neural Networks (very in-progress)
SystemVerilogVivadoComputer ArchitectureSystolic ArraysAXI-StreamQuestaSimPython
Projects
A collection of projects I've worked on, showcasing my skills and experience.
8-Way Set-Associative Cache Design
8-Way Set-Associative Cache Design in addition to a Fully-Associative and a Direct-Mapped Cache
SystemVerilogVivadoComputer ArchitectureQuestaSim
Floating-Point ALU for IEEE-754 Single-Precision Numbers
SystemVerilog-based design and FPGA implementation of a full-featured pipelined floating-point ALU
SystemVerilogRTL DesignIEEE-754Constrained-Random VerificationStatic Timing Analysis
6 Stage Pipeline RISC-V Cpu
SystemVerilog-based implementation of a RISC-V CPU core with a 6 stage pipeline and various pipeline optimizations
SystemVerilogRTL DesignComputer ArchitectureStatic Timing Analysis