Systolic Array-based Matrix Multiplier for Neural Networks
Systolic Array-based Matrix Multiplier for Neural Networks (very in-progress)
SystemVerilogVivadoComputer ArchitectureSystolic ArraysAXI-StreamQuestaSimPython
Hi, I'm Danton Klein
Computer Engineer | Previously at Microsoft and Motorola Solutions
🇺🇸 US
University of Florida ECE Graduate seeking a career as an RTL Design Engineer. Contact me at [email protected].
About Me
I’m an aspiring RTL design engineer with a Master’s in Electrical and Computer Engineering from the University of Florida. I specialized in RTL design with my coursework and projects emphasizing development for FPGAs. My biggests interests in computer engineering are computer architecture and accelerator design. Although my previous internships with Microsoft and Motorola Solutions were in EMC Compliance and RF testing, I realized my passions truly lie in digital design. When I’m not spending time learning and developing hardware you can find me going to the gym, exploring live music in Miami, or learning guitar.
Check Out My Latest Work
I've worked on a variety of RTL Design projects. Here is a sample of my projects.
8-Way Set-Associative Cache Design
8-Way Set-Associative Cache Design in addition to a Fully-Associative and a Direct-Mapped Cache
SystemVerilogVivadoComputer ArchitectureQuestaSim
Floating-Point ALU for IEEE-754 Single-Precision Numbers
SystemVerilog-based design and FPGA implementation of a full-featured pipelined floating-point ALU
SystemVerilogRTL DesignIEEE-754Constrained-Random VerificationStatic Timing Analysis
6 Stage Pipeline RISC-V Cpu
SystemVerilog-based implementation of a RISC-V CPU core with a 6 stage pipeline and various pipeline optimizations
SystemVerilogRTL DesignComputer ArchitectureStatic Timing Analysis
Work Experience
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Microsoft
Electrical Engineering Intern
Tested and improved the shielding of the XBOX Wireless Headset to bring electrical emissions to FCC specification. Automated Excel data collection with VBA scripting, saving technicians on average 2 hours per week. Drafted new test procedures to enable future aeronautical-grade device testing
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UF SHREC Lab
Research Assistant
Implemented pipelined Notch filter on an FPGA in SystemVerilog to filter ambient noise from a lightning detection system, improving usable data efficiency by 40%. Developed C++ programs for characterizing performance and scalability of different accelerator architectures.
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Motorola Solutions
Electrical Engineering Intern
Analyzed voltage timing characteristics of communication busses for the new FPGA on the APX Consolette Main Board revision to identify and diagnose issues in functionality. Performed microprocessor functionality testing for the new main board of APX Mobile O2 and O7 control heads
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Motorola Solutions
Electrical Engineering Intern
Worked within the Current Products Engineering group to maintain and update two-way radios regarding end-of-life part replacement. Operated instrumentation including waveform generators, signal analyzers, and radio test sets to test radios’ operation characteristics and to prepare them for mechanical and electrical stress testing. Conducted GPS testing for a new GPS IC for the APX 4500, APX 6500, and APX 8500 mobile radios by gathering fix values at different temperatures
Education
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University of Florida
Master of Science in Electrical and Computer Engineering
Aug 2023 - May 2025Focused on FPGA Design, Computer Architecture, Hardware Security, and VLSI Design. Graduated with a 3.89 gpa.
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University of Florida
Bachelor of Electrical Engineering
Aug 2020 - May 2024Focused on digital design and embedded software engineering. Graduated with honors with a 3.7 GPA.